1. Field of the Invention
The present invention generally relates to a method for forming a dual oxide layer, and more particularly to a method for forming a dual oxide layer having varying thicknesses by using a damage layer formed on the silicon substrate by dry etching, or a silicon nitride layer deposited on the silicon substrate.
2. Background of the Related Art
In the semiconductor industry, silicon dioxide (SiO2) is used in a variety of applications. Often, it is used as a dielectric or an insulative layer to electrically separate various regions or structures. Examples of use as a dielectric or an insulative layer include as a gate oxide on a MOS (Metal Oxide Semiconductor) device, as a dielectric of a capacitor, as an interlevel dielectric between metals, and for a field isolation.
When used as a gate oxide on a MOS device, the SiO2 layer needs to have excellent electrical characteristics. Particularly, as the mounting density of the semiconductor chip on the substrate has been improved, the thickness of the oxide layer has decreased, and the need for a gate oxide having excellent electrical characteristics and a thickness of 100 xc3x85 or less has arisen.
As the operational speed of electrical systems has increased, a merged IC, comprising a logic device, SRAM (Static Random Access Memory), DRAM (Dynamic RAM), and ROM (Read Only Memory) within one single chip, has been developed. Since each of the individual devices within the merged IC has a different operational speed and driving condition, each device requires a certain oxide layer thickness. This oxide layer, which has these varying thicknesses, is hereinafter referred to as a xe2x80x9cdual oxide layerxe2x80x9d, and is particularly used where an oxide layer with excellent electrical characteristics is required. For example, a merged IC, comprising a memory device and a logic device such as a microprocessor within one single chip, requires a dual oxide layer having excellent uniformity and a thickness of 100 xc3x85 or less. This requirement of a dual oxide layer also applies to microprocessors, such as the CPU of a computer system, having an operational speed of 700 MHZ or more.
In the dual oxide layer, a relatively thick part may be used as the gate oxide of a DRAM memory cell transistor. Since a voltage higher than a positive power supply voltage (Vcc) (for example, Vcc+2Vth, wherein Vth is a threshold voltage of the memory cell transistor) is provided to a gate electrode so as to drive word lines, the part having the greater thickness is used as the gate oxide of the DRAM.
The need for another oxide layer growth process to form the dual oxide layer is a very complicated procedure, resulting in reduced productivity of the procedure. Further, interaction among the oxide layer growth processes on one wafer makes it difficult to form the dual oxide layer having the designated thickness at a predetermined position. This interaction among the oxide layer growth processes is most severe during formation of an ultra thin dual oxide layer.
Accordingly, a need exists for a process to form the dual oxide layer using only one oxidation process.
Accordingly, an object of the present invention is to provide a method for forming a dual oxide layer having excellent thickness uniformity on a wafer using only one oxidation process.
Another object of the present invention is to provide a method for forming a dual oxide layer having enhanced electrical characteristics as well as a thickness of 100 xc3x85 or less.
Still another object of the present invention is to improve the productivity of merged IC devices by simplifying the procedure for forming a dual oxide layer.
To achieve these and other objects, in a first embodiment of the present invention, a damage layer is formed on the silicon substrate by dry etching a designated part of the silicon substrate, and a dual oxide layer is formed by using the properties of SiO2 that the oxide layer growth speed on the damage layer is slower than that on the silicon substrate. A pattern of the damage layer is defined by photolithography, and the damage layer having a depth of about 20 to 5,000 xc3x85 is formed by dry etching using CF4, CHF3, or Ar gas at a low pressure of 900 mTorr or less, or by dry etching using Cl2 or HBr.
In a preoxidation cleaning step for cleaning the substrate surface before forming the dual oxide layer on the silicon substrate on which the damage layer is formed, a solution, which contains NH4F, HF, and H2O, a standard solution which contains NH4OH, H2O2, and H2O, and/or HF are used. The oxidation method for growing the dual oxide layer may be ramping oxidation, pyrogenic wet oxidation, or HCl dry oxidation. The thickness of the dual oxide layer is determined by the depth of the damage layer, the preoxidation cleaning method, the oxidation method, etc.
In a second embodiment of the present invention, the dual oxide layer is formed by using the properties of Si3N4 that the oxide layer growth speed on the silicon nitride layer is slower than that on the silicon substrate. After depositing silicon nitride having a thickness of about 10 to 100 xc3x85 on the silicon substrate, a pattern of the silicon nitride layer is defined by photolithography and the silicon nitride layer is partially removed depending upon the pattern. After that, the silicon nitride layer is reduced to a thickness of about 3 to 50 xc3x85 by the preoxidation cleaning of the silicon substrate with a solution which contains NH4F, HF, and H2O, a standard solution, which contains NH4OH, H2O2, and H2O, and/or HF. Then the oxidation step for growing the dual oxide layer is carried out and thereby, a thinner part of the dual oxide layer is formed on the silicon nitride layer and a thicker part of the dual oxide layer is formed on the rest of the silicon substrate.